Historically the goal of polishing is to take out scratches from an otherwise planar surface. Here the polish rate at the sharp peaks is higher than at the indentations due to the stress concentrations at the peaks. This automatically leads to the elimination of the peaks.
Contrary to the above, the goal of polishing in the microelectronics industry is to planarize a scratch-free surface. Most often the surface morphology includes wide plateaus adjacent to wide valleys resulting from the conformal nature of most deposition processes when considered on a large scale. Since wide plateaus do not present significant stress concentrations, they do not polish much faster than the wide valleys. Consequently, polishing is inefficient in achieving planarization, and the starting surface morphology, (steps) is planarized only to a limited extent.
The wider the features, the more difficult planarization becomes. Since a soft pad is more conformal than a hard pad, its use practically excludes the possibility to planarize. The use of a hard (stiff) pad, while more favorable from a planarization point of view, still does not eliminate the problem, since while the degree of conformity decreases, it does not disappear. In addition, hard pads cause scratches on the surface with the abrasive or the polishing debris, which cannot be tolerated because these scratches in turn can cause shorts.
The requirement for planarity is the most stringent in the shallow trench isolation (STI) application of SiO.sub.2 because this feature is at the base, and every subsequent layer will replicate any non-planarity of the surface topography. Because of the lack of a truly planarizing polishing process, currently the problem is addressed by the deposition of "dummy structures" or "polish-stops" which elevate the valley areas to the height of the plateau areas. This requires extra design effort, extra patterning, extra deposition reactive ion etching and polishing steps. The total number of these expensive auxiliary steps often reaches six, where if planarization of the original polishing process were efficient, one step would suffice.
Concerning oxide planarization, it is important to appreciate the fact that oxide polishing results in an even lesser degree of planarization than does metal polish. This problem is reduced in interlevel dielectrics by increasing the initial thickness of the oxide, since planarization improves when an increasing amount is removed. While this approach increases the cost of planarization, the extent of planarization is still not good enough for very large scale integration schemes.